| Contact Information | |
| Name: | Nagendra Manickam |
| Email: | bit_nagendra (at) yahoo (dot) com [email concealed] |
| Location: | Atlanta, Georgia, United States |
| Resume | |
| Position/Title: | Sr. Security Engineer |
| Resume: |
Nagendra Manickam 678-481-3226 | bit_nagendra (at) yahoo (dot) com [email concealed] SUMMARY A Staff Software Security Engineer with over 10+ years of Extensive, Sophisticated and Valuable Experience in Managing, Designing, Developing and Testing Security Applications, Compilers, Debuggers, Embedded Software Projects. SKILLS · Design Experience in Software Security Design, Intrusion Detection, IDS/IPS Architectures, Security policies, Signatures, Vulnerability assessments, Security Incident Response, Penetration and Automated Testing. · Design and Implemented Firewall, Packet Filter, Event Filter Rules and IDS/IPS Signatures. · Strong Knowledge of Host/Network Vulnerabilities, Exploits, Attacks, Firewalls, VPN. · Exposure to Security tools (Snort, Netcat, Tcpdump), Risk Analysis and Management. · Extensive Experience working with of Various Internet Protocols (TCP/IP, DNS, HTTP, UDP, DNS, SMTP, SIP). · Fundamental knowledge of: Access control, Encryption, Security event log analysis. · Clear and demonstrable knowledge of the Integration of security in the SDLC. · Strong Knowledge of Finite Automata, Regular Expressions and Compiler Principle Techniques. · Experience working with Intel x86 processors and developed Low Level Software for Intel 32- bit Processors. Implemented Source Level Debugger for Intel Based Processors across multiple platforms. · Extensive Programming experience using C (Pointer Manipulation, Linked List Handling and Data Structures), C++, X86 Assembly (Interrupt Handlers, Protected Mode Programming). Comfortable with Standard Template Library (STL) with C++. WORK EXPERIENCE · IBM Internet Security Systems, Atlanta, Georgia (www.ibm.com) as Staff Software Security Engineer from March’ 2005 to the date. · American Mega trends, Inc., Atlanta, Georgia (www.ami.com) as Software Engineer from June’ 2000 to March 2005. · Wipro Technologies Pvt Ltd, Bangalore, India (www.wipro.com) as Senior Software Engineer from Jan’ 2000 to May 2000. · Dacs Software Pvt Ltd, Bangalore, India as Software Engineer from October 1998 to Jan 2000. EDUCATION BS in Computer Science Engineering, GPA 4.0/4.0, Bangalore University, BIT–Bangalore, India. PROJECTS/ WORK EXPERIENCE IBM Internet Security Systems March 2005 – Present Project: Multi-Platform Embedded Security Protocol Analysis Module Location: Atlanta, Georgia Position: Senior Developer and Lead Description: The Protocol Analysis Module (PAM) combines advanced protocol Anomaly detection with proven signature-based detection technology to interpret network activity and detect attacks at all layers of the protocol stack. PAM is one of the core components that are used in almost all of ISS Products (Proventia G/M, Real Secure, Site Protector, Black Ice). OS: Windows, Linux Language: C, C++ with STL, X86 Assembly Language Responsibilities: · Design and Implementation of Parsers, new features for improving performance and efficiency. · Working closely with support team and customers to handle critical escalations. · Analyzing large volumes of IDS, Firewalls, Proxies and Network data. · Collecting, summarizing, and analyzing Internet traffic and incident data for security trends. · Review and monitor firewalls, IDS and system logs to investigate security anomalies · Responsible for investigating and responding to security incidents · Proactively worked with cross-functional teams. · Research, Reverse engineering about the exploits, attacks and vulnerabilities. · Implemented of SNORT, Net flow with the PAM. · Ported the PAM source code from VC 6.0 compiler to VS 2008. · Identified Security risks, Threats and vulnerabilities of networks, systems, applications and new technology initiatives. · Developed tests for firewalls and software deployment tools. · Evaluate new tools, implement test tools for regression. · Train Sales Engineers about ISS Products. AMERICAN MEGATRENDS INC March 2001 – March 2005 Project: Assembly Source Level Debugger for BIOS Location: Atlanta, Georgia Position: Developer and Team Lead Description: The Assembly source level debugger consists of two components HOST and Target. The host and target are connected via wired serial cable. Target modules are embedded inside the bios during the BIOS build Process. Host program consists of user interface to display the disassembly window, source window, registers view, symbol watch, memory window, setting Breakpoints, PCI view, CMOS view, indexed IO view, functions view etc. Debugger is capable of debugging over LAN called as remote debugging so that it facilities of debugging the target system irrespective of location of target BIOS. Target modules consist of two layers debug and serial transport layer. Host program consists of GUI, core components, debug and transport Layer. OS: Windows 2000 Language: C++ with STL, X86 Assembly Language Responsibilities: · Design, coding, testing of debug layer, serial transport layer for the target side. · Design, coding, testing of core components, debug Layer, serial transport layer for host. · Feature Implementation such as registers (general purpose, MSR, MMX, control and debug Registers), CMOS, PCI, indexed IO, break on checkpoint, time points, view points, memory, macro commands etc., · Implementations of software, hardware breakpoints, Break on IO access, break on Memory Read/ Write, Source level debugging, step-In, step-over. · Symbol watch implementation using 16-bit code view Information File for all user defined data types. · Implementation of function view, global symbols, remote debugging over LAN, flashing. · Testing of the complete functionality. AMERICAN MEGATRENDS INC Feb 2003 – March 2005 Project: 32 bit C Source Level Application Debugger for Intel Tiano using Microsoft WinDbg. Location: Atlanta, Georgia Position: Developer Description: Tiano debugger consists of two components Target and HOST. Target components are embedded inside BIOS during the build. The Host and Target are connected through wired serial cable. Platform builder’s extended debugging interface (EXDI) enables the end user to control and debug a target device using a driver and serial cable. EXDI driver is a component object model (COM) server that allows target to communicate with platform builder. EXDI driver exposes the IeXdiServer interface and the IeXdiCPUContent interface for the X86 microprocessor as IeXdiX86Content interface. Target consists of totally four components out of which two are provided by EFI for creation of debugger support namely debug support protocol and debug port protocol. Debug support manages the processor's context via caller-installable exception handlers. Debug port protocol is used for communication between host and target such as serial port. Other two layers are debug layer and transport layer that provides core functionality of the target. The Host consists of EXDI driver, translate layer, debug layer and Transport Layer. The EXDI plug-ins is developed to implement our own functionality. OS: Windows 2000 Language: C, C++ and X86 Assembly Language. Responsibilities: · Design, Implementation, testing of debug and transport layer for target. · Design, Implementation, testing of translate layer interface, debug and transport layer of the host. · Implementation of Extension commands via EXDI plug-In. · Implementations of software, hardware breakpoints, Break on IO access, break on Memory Read/Write, Source level debugging, step-In, step-over. · Testing functionality of EFI debugger. AMERICAN MEGATRENDS INC Feb 2002 – Oct 2002 Project: 32 bit C Source Level Application Debugger for EFI (Extensible Firmware Interface) using Microsoft WinDbg. Location: Atlanta, Georgia Position: Developer Description: The EFI debugger consists of two components Target and HOST. The Host and Target are connected through wired serial cable. Platform builder’s Extended Debugging Interface (EXDI) enables the end user to control and debug a target device using a driver and serial cable. EXDI driver is a component object model (COM) server that allows target to communicate with platform builder. EXDI driver exposes the IeXdiServer interface and the IeXdiCPUContent interface for the X86 microprocessor as IeXdiX86Content interface. Target consists of totally four components out of which two are provided by EFI for creation of debugger support namely debug support protocol and debug port protocol. Debug support manages the processor's context via caller-installable exception handlers. Debug port protocol is used for communication between host and target such as serial port. Other two layers are debug layer and transport layer that provides core functionality of the target. The Host consists of EXDI driver, translate layer, debug layer and transport layer. The EXDI plug-ins is developed to implement our own functionality. OS: Windows 2000 Language: C, C++ and X86 Assembly Language. Responsibilities: · Design, Implementation, testing of debug and transport layer for target. · Design, Implementation, testing of translate layer interface, debug and transport layer of the host. · Implementation of Extension commands via EXDI plug-In. · Implementations of software, hardware breakpoints, Break on IO access, break on Memory Read/Write, Source level debugging, step-In, step-over. · Testing functionality of EFI debugger. AMERICAN MEGATRENDS INC JUNE 2000 – FEB 2001 Project: Porting of Generic BIOS for Intel 815 (Solano) Chipset. Location: Atlanta, Georgia Description: Porting of Generic Bios involves programming the general configuration registers of ICH (I/O controller Hub) depending on the chipset. The chipset initialization tables are set up according to the specifications. The OEM porting hooks are ported according to the specifications of ICH. The generic chipset access routines are modified for the Solano chipset. The E-modules such as SMI support and USB support is also ported. The Super I/O IT8712F is programmed depending upon the specifications. The IRQ routing table is updated depending on the built-in P2P Bridges and PCI Slots and onboard devices located behind those bridges. The hardware compatibility tests are conducted to check the yellow devices (faulty devices). Language: X86 Assembly Language Responsibilities: · Porting of OEM hooks. · Porting of E-Modules. · Programming chipset initialization and ICH. · Testing of the bios running automated tests and manual tests WIPRO TECHNOLOGIES PVT LTD, INDIA Jan 2000 – May 2000 Project: TCP/IP Stack for Embedded Systems Location: Bangalore, India Position: Team Member OS: Linux Language: C Responsibilities: · Maintenance, enhancement and testing of address resolution protocol (ARP) according to RFC. · Maintenance, enhancement and testing of reverse address resolution protocol (RARP) according to RFC. DACS SOFTWARE PVT LTD, INDIA May 1999 – Jan 2000 Project: Expression Evaluator for the C Source Level Debugger Location: Bangalore, India Position: Team Member Team Size: Two Client: Zilog Inc USA Description: The Expression Evaluator provides various provisions such as displaying the values of the selected programmer defined variables. The Expression Evaluator facility provided by the SLD allows the user to enter an expression through the CLI/GUI and the SLD evaluates this expression. This expression in the context of the expression evaluation in a debugger is an address with the associated type. The value of the expression is obtained from the contents of a determinable amount of memory (based on the type of the Expression) at that address. The evaluation of the expression is formed out of the program variable elements present in the source level debugger. The expression evaluator in the process of evaluating the expression reads the object file for evaluating the attributes of the symbols in the expression, as well as the target through a set of Interfaces provided by the source level debugger. Hardware: Pentium -II OS: Windows NT Language: C Tools: LEX, YACC Responsibilities: · Design, Implementation and testing of Lexical Analyzer · Input file description of the YACC parser. · Interfaces for the reading from the COFF file format. · Design of retrieving information from COFF file for the entire user defined data types. · Testing of the expression evaluator DACS SOFTWARE PVT LTD, INDIA Oct 1998 – Apr 1999 Project: Development of Z182 Compiler Location: Bangalore, India Position: Team Member Team Size: Two Client: Zilog Inc USA Description: Z182 Compiler is ported from the GNU C compiler source code. Z182 compiler provides a freestanding implementation with ANSI C compliance. The compiler accepts the programs, which confine the features of the ANSI standard Library. The front end of the GNUC C remains the same. Only the back end part of the GNUCC is altered. The machine description of the Z182 processor is provided in the form of RTL description to the back end of the GNU C compiler. The machine description has two parts: a file of Instruction patterns and a C header file consisting of the macro definitions. Hardware: Pentium -II OS: Linux Language: C, RTL (Register Transfer language) Responsibilities: · Writing RTL expressions · Testing the RTL expressions. · Verifying the Correctness of RTL expressions. |
